The present invention relates in general to communication and signal processing systems and components therefor, and is particularly directed to an external programming circuit that is adapted to be coupled to an input/output pin shared by a programmable device, such as memory device, with other system functions, and is operative to controllably generate an electrical stimulus including a programming voltage, respective high and low logic levels, and a high impedance state, and thereby place the memory device in a selected one of a plurality electrical states, without affecting normal device operation.
A wide variety of electronic devices commonly contain a microprocessor or microcontroller having internal and/or external memory. Current memory device implementations are typically non-volatile devices, such as electrically erasable programmable read only memory (EEPROM) devices, which can be programmed or reprogrammed by the application of an electrical stimulus (in contrast with older EPROM devices that required the application of high intensity ultraviolet light through a quartz window in the package containing the memory chip).
The electrical stimulus that is used to program an EEPROM is customarily generated using an in-system programming (ISP) mode, in which an elevated voltage that exceeds the typical operating voltage of the device is coupled to one or more of the device interface pins, while data is applied to the device through other pins. ISP mode has advantages over traditional programming schemes in all stages of memory life including product development, manufacturing and customer service. A principal advantage of ISP mode is the ability to program or reprogram the device without removing (e.g., unsoldering) the memory device from its circuit board.
However, interfacing ISP mode signals from the system in which the memory device is installed is a non-trivial function, since the one or more pins used for programming such (EEPROM) memory devices are also shared with other (input/output (I/O) functions, such coupling to an external clock oscillator""s quartz crystal element), in order to constrain package size. In addition to driving a shared programming pin with a high programming voltage during a typical programming operation, it may also be necessary to drive the pin with a high logic level, a low logic level, and a high impedance state. This has conventionally been accomplished by using a dedicated programming voltage that is switched into the device by an analog switch or the like.
In accordance with the present invention, the desire to perform in-system programming and/or driving of a device, such as an EEPROM, with differentially valued stimuli, without affecting normal device operation and without the need for complicated and expensive programming hardware, is successfully addressed by a new and improved, relatively inexpensive programming circuit architecture, which is controllably operative to generate a programming voltage only when necessary, while also being capable of selectively supplying each of high and low logic levels, as well as driving the device to a high impedance state.
For this purpose, the selective programming circuit architecture of the present invention comprises a switchmode power converter, a linear regulator, and an associated set of steering transistors, coupled in circuit with high and low voltage supply terminals and an output node, which outputs an electrical stimulus for externally establishing the electrical state of a programmable device. As will be described, the switchmode power converter may be configured as a pulse width modulated (PWM) power boost converter, which may comprise the power stage of a PWM boost DCxe2x80x94DC converter, and is used to generate the required programming voltage, which exceeds the typical operating voltage of the device. The programming voltage is generated by the PWM boost converter only when required for programming the device.
The PWM boost converter includes a controlled switching device such as a field effect transistor (FET), having its source-drain path coupled in circuit with an inductor between respective power supply terminals. A rectifier is coupled between the inductor and an electrical stimulus coupling path to the linear regulator. An energy storage capacitor is coupled between the stimulus coupling path and ground, and is used to store energy supplied from the power source and the inductor, when the PWM boost circuit""s FET is in the OFF state. When the FET is in the ON state, electrical energy is stored in the inductor.
The linear regulator includes a transistor having its collector-emitter path coupled between the stimulus coupling path from the PWM boost converter and the output node, as well as to a voltage divider network that is coupled to the control input of a precision shunt regulator device which, in turn, is coupled to the base of the transistor to establish the value of a programming voltage to be selectively applied from the output node to the device. The base of the linear regulator transistor is controllably coupled to ground through the collector-emitter path of a second (or xe2x80x98highxe2x80x99) transistor. This second transistor enables the high impedance state and logic high level state. The linear regulator""s output node is controllably coupled to ground through the collector-emitter path of a third (or xe2x80x98lowxe2x80x99) transistor. This third transistor enables the logic low level state. The output node is coupled to a programming (I/O) pin of the device.
To generate the programming voltage, the high and low transistors are turned OFF, while a PWM signal is supplied to the PWM FET. The boost voltage will therefore be coupled through the linear regulator transistor to the output node. To generate a high logic level voltage, both high and low steering transistors are turned OFF, as in the programming mode. In addition, the PWM FET is turned OFF. As a result, a DC coupling path is provided to the output node from the supply terminal VCC through the PWM converter and the linear regulator transistor. The voltage supplied by the output node to a device I/O pin is therefore equal to the supply voltage VCC minus the voltage drops of the PWM converter""s diode and the base-emitter junction of the linear regulator transistor.
If this slightly reduced voltage is not sufficient to provide the desired high logic level voltage at the output node, an optional resistor may be connected in a manner to compensate for either or both of the voltage drops. The linear regulator may be also be augmented to regulate the logic high voltage level at a precise value, by coupling the boosted voltage to the collector of the regulator""s transistor for both the programming mode and logic high level mode. This may be readily accomplished by connecting a series resistor and auxiliary transistor in parallel with one of resistors of the voltage dividing network, and thus forcing the set point of the linear regulator to either the logic high level voltage or the higher programming voltage.
To generate a low logic level voltage, both of the high and low steering transistors are turned ON, while the PWM converter""s FET is turned OFF. With the high steering transistor turned ON, its collector-emitter path provides ground potential to the linear regulator""s base transistor, causing the regulator transistor to be by-passed, so as to interrupt the DC coupling path from the output node from the VCC supply. Additionally, with the low steering transistor turned ON, the output node is directly coupled to ground through the collector-emitter path of the low steering transistor.
In order to place the output node in a high impedance state, the PWM regulator""s switching FET and the low steering transistor are turned OFF, while the high steering transistor is turned ON. Since the high steering transistor is turned ON, the base-emitter junction of the linear regulator""s transistor will be off, or slightly reverse biased, so that the output node will see only the impedance provided by the voltage divider network and the reverse biased base-emitter junction of the regulator transistor.